This invention is in the field of amplifiers, and is more specifically directed to preamplifiers for magnetoresistive heads as used in a disk drive system.
Continuing progress toward higher performance yet less expensive personal computers, including both desktop workstations and portable computers, has resulted in large part from advances in nonvolatile data storage technology. As is well known in the art, the capacity of conventional disk drives has greatly increased over recent years, at ever decreasing cost per megabit. This capacity increase is directly related to improvements in the density with which data can be stored in a magnetic disk drive, particularly in “hard” disk drives (i.e., disk drives in which the magnetic disk is not removable from the location of the read/write heads).
In conventional magnetic disk drives, the writing and reading of stored data is carried out by way of near-field magnetic processes. To write data, ferromagnetic domains at the disk surface are selectively oriented by applying a magnetic field in close proximity to the disk surface. One type of conventional write head is the well-known inductive writer, which includes an electromagnet having a gap that can be positioned near the magnetic disk surface. The electromagnet is selectively energized to establish a magnetic field, at the gap, that is strong enough to define a magnetic “transition pattern” of the desired polarity at the addressed location of the disk surface. Data is read from the disk by sensing the polarity of the magnetic field established by these magnetic transition patterns. Conventional read heads include inductive heads consisting of an electromagnet (which may be the same electromagnet used to write data) in which a current is induced by the magnetic fields at the disk surface; more recently, read heads are implemented by a magnetoresistive (MR) head having a resistance that varies with the polarity of the magnetic field.
As is fundamental in the art, MR heads are biased to a steady-state operating point, so that the variations in the resistance of the MR head, due to the data-dependent varying magnetic field as the head travels along the disk surface, appear as small signal variations on this steady-state operation. These small signal variations are amplified by a preamplifier, and with the amplified signals forwarded along the data channel of the disk drive system. An example of a bias circuit for an MR head in a modern disk drive system is described in my copending and commonly assigned U.S. patent application Ser. No. 11/344,037, filed Jan. 31, 2006, and entitled “Bias Circuit for a Magnetoresistive Preamplifier Circuit”.
FIG. 1 illustrates an example of a conventional preamplifier circuit as used in modern disk drive systems. Preamplifier 2 of FIG. 1 corresponds to the first amplification stage in the disk drive preamplifier, and as such has inputs HEADP, HEADN for receiving the voltage across the MR read head. In conventional preamplifier 2, DC offset voltage across inputs HEADP, HEADN is removed by cross-coupled differential transistor pairs. More specifically, input HEADP is connected to the base of npn transistor 2a, which has its collector coupled through resistor R1 to the Vcc power supply. Input HEADP is also capacitively coupled, via capacitor C1b, to the base of npn transistor 3b in another differential transistor pair; transistor 3b has its collector biased to the Vcc power supply via resistor R4. Conversely, input HEADN is connected to the base of npn transistor 3a, which has its collector biased to Vcc through resistor R3. The emitters of transistors 3a, 3b are connected together and to the Vee power supply via current source 7, which sources a current ITAIL. Similarly, input HEADN is capacitively coupled to the base of npn transistor 2b, which has its collector biased to Vcc via resistor R2. The emitters of transistors 2a, 2b are connected in common, and to the Vee power supply via current source 6, which also sources current ITAIL. Transconductance (gm) stage 5a receives the voltage at the collector of transistor 2a, at a negative input, and drives a current into the base of transistor 2b corresponding to the difference between this collector voltage and a reference voltage REF. Similarly, gm stage 5b receives a voltage from the collector of transistor 3a at an inverting input, and compares that voltage with reference voltage REF to produce a bias current into the base of transistor 3b. 
In operation, gm stages 5a, 5b block the DC bias voltage at the MR head, which of course is applied to inputs HEADP, HEADN, from being reflected at the output of preamplifier 2. For example, if the voltage at input HEADP has a relatively high DC steady state value, that voltage will tend to turn transistor 2a on relatively hard, which pulls the voltage at the collector of transistor 2a lower because of the voltage drop across resistor R1. This DC level is compensated by gm stage 5a which, in response to the relatively low voltage at the collector of transistor 2a as applied to its inverting input, will source more current into the base of transistor 2b; because the sum of the emitter currents of transistors 2a, 2b are fixed to current ITAIL by current source 6, this higher bias current into the base of transistor 2b will reduce the current through transistor 2a, permitting its collector voltage to rise back to a stable level (determined by reference voltage REF). Similar operation is provided by gm stage 5b, in blocking the DC levels at input HEADN from affecting circuit operation.
Conventional preamplifier 2 of FIG. 1 provides a differential output stage at its outputs OUTP, OUTN. Output OUTP is taken at the emitter of transistor 4a, which has its base connected to the collector of transistor 2a, and its collector biased directly to the Vcc power supply, in emitter follower fashion. Resistor R5 connects the emitter of transistor 4a to input HEADP, and through current source 8a to the Vee power supply. Similarly, transistor 4b has its collector biased directly to Vcc, and its emitter connected to input HEADN via resistor R6; this emitter node is also biased to the Vee power supply via current source 8b. Output OUTN is taken from the emitter of transistor 4b, in emitter follower fashion. Outputs OUTP, OUTN are forwarded to the next gain stage in the disk drive preamplifier.
According to this construction, the signal at inputs HEADP, HEADN is amplified at the collector of transistors 2a, 2b, respectively, and output to nodes OUTP, OUTN via the emitter followers of transistor 4a, 4b, respectively. On each side of this circuit, a feedback loop is provided by the operation of resistor R1 through transistor 4a (for input HEADP) and by operation of resistor R3 through transistor 4b (for input HEADN). In effect, the amplifier and feedback portions of this preamplifier circuit can be considered as an inverting amplifier with a resistor (R5, R6) from the output back to the input. Those skilled in the art will therefore readily derive the input impedance Zin as:
      Z    in    =            R      f              k      +      1      where Rf is the resistance of the corresponding resistor R5, R6, and where k is the gain of the amplifier established by transistor 2a, 2b and corresponding collector resistor R1, R3, respectively. In conventional preamplifier circuits for disk drive systems, this input impedance Zin is typically matched to the impedance of the transmission line of the connection between the MR head and input nodes HEADP, HEADN. This input impedance Zin is typically determined by design and characterization.
It has been observed, in connection with this invention, that the use of a fixed input impedance Zin is not optimal in many disk drive applications, however. For example, the same preamplifier integrated circuit may be used over a wide range of system applications, with different conductor lengths and characteristics possible, depending on the system application. These differing system realizations can easily result in the transmission line impedance, between the MR head and the preamplifier, not matching the input impedance of the preamplifier circuit itself. This mismatch will of course result in reflections and other degradation of the signal from the MR head, which can lead to read errors and poor performance. In addition, it has been observed, in connection with this invention, that this input impedance can be somewhat frequency dependent. As such, variations in the signal frequency from the MR head may not be accurately sensed by the preamplifier, at those frequencies with mismatched input impedance.